Adaptative Techniques to Reduce Power in Digital Circuits

Adaptative Techniques to Reduce Power in Digital Circuits

CMOS chips are engineered with sufficient performance margins to ensure that they meet the target performance under worst case operating conditions. Consequently, excess power is consumed for most cases when the operating conditions are more benign. This article will review a suite of dynamic power minimization techniques, which have been recently developed to reduce power consumption based on ...

Emerging Power-Gating Techniques for Low Power Digital Circuits

Subthreshold leakage control techniques for low power digital circuits

Scaling and power reduction trends in future technologies will cause subthreshold leakage currents to become an increasingly large component of total power dissipation. As a result, new techniques are needed in order to provide high performance and low power circuit operation. This dissertation develops new circuit techniques that exploit dual threshold voltages and body biasing in order to red...

Low Power Design Techniques for Digital Logic Circuits

With the rapid increase in the density and the size of chips and systems, area and power dissipation become critical concern in Very Large Scale Integrated (VLSI) circuit design. Low power design techniques are essential for today's VLSI industry. The history of symbolic logic and some typical techniques for finite state machine (FSM) logic synthesis are reviewed. The state assignment is used t...

Using Dual-Supply, Dual-Threshold and Transistor Sizing to Reduce Power in Digital Integrated Circuits

(Date)-ii-Abstract In both high and low performance circuits, both active and leakage control of power consumption is critical. This research focuses on the use of multiple threshold voltages, multiple supply voltages and transistor sizing to reduce power in digital circuits. Non-critical paths are slowed down by either raising the threshold voltage, lowering the supply, downsizing gates, or a ...